IEEE 2012 2013 DATA MINING TOPICS AND PROJECTS TITLES WITH ABSTRACT FREE DOWNLOAD

IEEE 2012 2013 JAVA DATA MINING FREE DOWNLOAD

1. IR-Tree: An Efficient Index for Geographic Document Search
2. A Fuzzy Self-Constructing Feature Clustering Algorithm for Text Classification
3. Anonymous Publication of Sensitive Transactional Data
4. Cosdes: A Collaborative Spam Detection System with a Novel
5. Efficient Relevance Feedback for Content-Based Image Retrieval by Mining User
Navigation Patterns
6. A Personalized Ontology Model for Web Information Gathering
7. A Unified Probabilistic Framework for Name Disambiguation in Digital Library
8. Improving Aggregate Recommendation Diversity Using Ranking-Based Techniques
9. One Size Does Not Fit All: Towards User- and Query-Dependent Ranking For Web
Databases
10. Effective Navigation of Query Results Based on Concept Hierarchies
11. Data Leakage Detection
12. Bridging Domains Using World Wide Knowledge for Transfer Learning
13. TEXT: Automatic Template Extraction from Heterogeneous Web Pages
14. Mining Web Graphs for Recommendations
15. Horizontal Aggregations in SQL to Prepare Data Sets for Data Mining Analysis
16. Document Clustering in Correlations Similarity Measure Space
17. Scalable Learning of Collective Behavior
18. Query Planning for Continuous Aggregation Queries over a Network of Data
Aggregators

19. A Query Formulation Language for the Data Web

20. Scalable Scheduling of Updates in Streaming Data Warehouses
21. Publishing Search Logs - A Comparative Study of Privacy Guarantees
22. Optimal Service Pricing for a Cloud Cache
23. On the Complexity of View Update Analysis and its Application to Annotation
Propagation
24. Exploring Application-Level Semantics for Data Compression .
25. A Link Analysis Extension of Correspondence Analysis for Mining Relational Databases
26. Exploring Application-Level Semantics for Data Compression
27. Horizontal Aggregations in SQL to Prepare Data Sets for Data Mining Analysis
28. Document Clustering in Correlations Similarity Measure Space
29. Scalable Learning of Collective Behavior

30. Query Planning for Continuous Aggregation Queries over a Network of Data
Aggregators
31. A Query Formulation Language for the Scalable Scheduling of Updates in Streaming
Data Warehouses
32. Publishing Search Logs - A Comparative Study of Privacy Guarantees
33. Optimal Service Pricing for a Cloud Cache
34. On the Complexity of View Update Analysis and its Application to Annotation
Propagation
35. Exploring Application-Level Semantics for Data Compression .
36. A Link Analysis Extension of Correspondence Analysis for Mining Relational Databases
37. Exploring Application-Level Semantics for Data Compression

IEEE 2012 2013 JAVA NETWORKING

1. A Simple Model for Chunk-Scheduling Strategies in P2P Streaming
2. Optimal Anycast Technique for Delay-Sensitive
3. Energy-Constrained Asynchronous Sensor Networks
4. Energy-Efficient Protocol for Cooperative Networks
5. Jamming-Aware Traffic Allocation for Multiple-Path
6. Routing Using Portfolio Selection
7. Load Balance with Imperfect Information in Structured Peer-to-Peer Systems
8. FDAC: Toward Fine-Grained Distributed Data Access Control in Wireless Sensor
Networks
9. Site-Based Partitioning and Repartitioning
10. Techniques for Parallel PageRank Computation
11. Exploiting Dynamic Resource Allocation for Efficient
12. Parallel Data Processing in the Cloud
13. Data integrity proofs in cloud storage
14. Live Streaming with Receiver-based Peer-division Multiplexing
15. Continuous Neighbor Discovery in Asynchronous Sensor Networks
16. Jamming-Aware Traffic Allocation for Multiple-Path Routing Using Portfolio Selection 

IEEE 2012 2013 JAVA WIRELESS COMMUNICATION

1. Network Coding Based Privacy Preservation against Traffic Analysis in Multi-hop
Wireless Networks
2. Throughput Optimization in High Speed Downlink Packet Access (HSDPA)

3. Distributed Adaptation of Quantized Feedback for Downlink Network MIMO Systems
4. A Spatiotemporal Approach for Secure Range Queries in Tiered Sensor Networks

IEEE 2012  2013 JAVA DEPENDABLE AND SECURE COMPUTING

1. A Policy Enforcing Mechanism for Trusted Ad Hoc Networks
2. A Tamper-Resistant Programming Language System
3. Adaptive Fault Tolerant QoS Control Algorithms for Maximizing System Lifetime of
Query-Based Wireless Sensor Networks
4. Robust Correlation of Encrypted Attack Traffic through Stepping Stones by Flow
Watermarking
5. Nymble: Blocking Misbehaving Users in Anonymizing Networks
6. Privacy-Preserving Updates to Anonymous and Confidential Databases
7. Dynamics of Malware Spread in Decentralized Peerto- Peer Networks

IEEE 2012  2013 JAVA SERVICE COMPUTING

Vulnerability Analysis in SOA-Based Business Processes

IEEE 2012 2013 JAVA NETWORK SECURITY

Improved Division by Invariant Integers

IEEE 2012 2013 JAVA MOBILE COMPUTING

A Privacy-Preserving Location Monitoring System for Wireless Sensor Networks

IEEE 2012  2013 JAVA PARALLEL AND DISTRIBUTED SYSTEMS

Rumor Riding: Anonymizing Unstructured Peer-to- Peer Systems

IEEE 2012 2013 JAVA IMAGE PROCESSING

1. Color Extended Visual Cryptography Using Error Diffusion processing
2. Computational Perceptual Features for Texture Representation and Retrieval
3. Lossy Compression and Iterative Reconstruction for Encrypted Image
4. Road extraction using K-Means Clustering and morphological operations
5. Embedded extended visual cryptographic schemes

UPLOADED BY ROBIN ALEX

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CREDIT CARD PAYMENT PROCESSING MINI PROJECTS WITH DOCUMENTATION

REGISTRATION SYSTEM, Banker database system, DATABASE TYPE PROJECTS, VB PROJECTS, JAVA PROJECTS, Java Script, MINI PROJECTS, IEEE CSE Projects, CSE, IEEE IT PROJECTS, IT, FINAL YEAR PROJECTS, OTHER PROJECTS, HOW TO,

CREDIT CARD PAYMENT PROCESSING

7. Products to Customer

MERCHANT

3. Credit card information sent to principal bank

BRIEF DETAILS OF DIAGRAM

1. Customer pays for online purchase by credit card.

2. E business processes credit card using payment processing software.

3. Credit card information sent to principal bank holding merchant account.

4. Principal bank sends request to card issuing bank.

5. Card issuing bank accepts or declines and sends transaction back to

Principal bank

6. Principal bank sends transaction back to merchant.

7. Merchant fulfilled the order and consumer received the products.

MODULAR DESCRIPTION

Credit Card Banking (CCB) has the following modules namely:

¨                  SignUp Module

¨                  Accounts Module

¨                  Login Module

¨                  Card Module   

Signup Module:

                 

                  The SignUp Module is used in Personal Information details.If you collect all the inputs when you press the submit button in the main page and checked it the database. Your details are store for SignUp module.

Accounts Module:

                  The Accounts Module is used to enter the accounts details with checked in Accounts number and amount. It is collected for the database access.

Login Module:

                 

                  The Login Module is used in existing and new user details. If you enter user name and password then log is in correct for the option to proceed.

Card Module:

                  The Card Module deals with Card Selection, Card Validation and Limit Validation.

SYSTEM REQUIREMENTS

WORKING ENVIRONMENT

                       

                        Windows 98

Software Requirements:

              Web Server -        JavaWebServer2.0

              Front end     -        HTML

              Script          -        JavaScript

              Middle Tier  -        Servlets2.0

              Back end     -        MS ACCESS

Minimum Hardware Requirements:

              Processor    -        Intel inside Pentium-II

              Hard Disk    -        20GB

              RAM           -        128MB SDRAM

              CD Drive     -        52x Samsung

              Floppy drive          -        1.44 MB Sony


Click here to download

Link---->Part 01 

Link--->Part 02

Abstract The Card Management System is a Windows based application that takes care of the complete internal Card Processing activities of a Bank (management and maintenance of cards). It is suitable for the management of Debit Cards, Credit Cards as well as Smart Cards. It mainly involves the maintenance and management of card - related information in a Bank. This product caters to all the Credit, Debit and Smart Card based functions of a bank like Registration of Customers for card issue, Opening Card Accounts for the registered customer, Creation of Cards for registered customers, Hot Carding, making the Card ready for Embossing by creation of Card Data file etc. The Card Management System could interact with an external Card Transaction System, thereby making the Card-related information maintained by the bank, up-to-date. The purpose is to build a Card Management System which provides complete card processing, to meet the needs of full-fledged Credit card and Debit card based ATM or Point of Sale network. Proposed System The proposed system is designed to change the existing system into more effective. It makes the customer easier to get a cash. The Card Management System could interact with an external Card Transaction System, thereby making the Card-related information maintained by the bank, up-to-date. The purpose is to build a Card Management System which provides complete card processing, to meet the needs of full-fledged Credit card and Debit card based ATM or Point of Sale network. Customer can apply for credit card and know his eligibility from his own place just by giving his personal details. Everything comes to his door. Person comes to collect the required documents. Verification and other process will be finished within 5 days and customer is intimated about the sanctioned loan amount and EMI that he has to pay. Modules •  Admin Module •  Employee Module •  Credit Card Creation •  Loan Module Hardware Specification Processor : Pentium III Speed - 1.1 Ghz RAM - 256 MB(min) Hard Disk - 20 GB Floppy Drive - 1.44 MB Key Board - Standard Windows Keyboard Mouse - Two or Three Button Mouse Monitor - SVGA Software Specification OPERATING SYSTEM :Windows 2000. Technology : .NET DATABAS : SQLServer 7.1

Click here to download

Link---->Part 01 

Link--->Part 02

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online shopping project source code free download

Dear Prof/Stud/Friends
                                online shopping project source code free download in java and C#
                               

Shopping Cart Application in C#

for more information complete application

shopping cart application

c# project

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bmharwani

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Symposium Registration Software DOCUMENTATION AND SOURCE CODE

Language: Visual Basic

This is a simple symposium registration software.Password:it

registration system

KEYWORDS:
VB PROJECTS,REGISTRATION SYSTEM, IEEE CSE Projects, IEEE PROJECTS, MINI PROJECTS, FINAL YEAR PROJECTS, IT, mca, IEEE IT PROJECTS, ALL DEPT, MYSQL PROJECTS, NETWORK PROJECTS, C#.NET, DOMAIN, 

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Latest Bio Medical Projects titles free download with documentation and reports

Biomedical Projects, FINAL YEAR PROJECTS, AI PROJECTS, IMAGE PROCESSING,

 

1. Latest Bio Medical Projects free download with documentation and reports
2. Device to Measure the Stiffness of Intact Mouse Heart 
3. Fetal Heart Beat Monitor 
4. Abdominal Aortic Aneurysm Pressure Monitor 
5. Multi Channel Temperature Monitor for Surgery 
6. An MRI Compatible Infusion Pump 
7. Portable Patient Training Device For Lung Cancer Treatment 
8. Robotic Image Guide Biopsy 
9. Probing the Experience of Pain 
10. Assessment of Intrapleural Pressure Changes 
11. Portable Computer-Aided Drug Dispenser 
12. Eye Movement Measurement In MRI 
13. Automatic Metered Dose Inhalant (MDI) 
14. Mechanical Testing System Coupled with an Environmental Chamber 
15. Tongue Pressure Sensor System 
16. A model of CSF flow in the Human Cardio vertertebral Junction 
17. Biofeedback/Stress Management 
18. Epilepsy Monitor 
19. Sonography 
20. Eye Drop Device 
21. Development of an Exhaled Breath Condensate System for use During Exercise 
22. Hospital Connecting System 
23. Use of intravascular ultrasound probe to improve biopsy yield 
24. Ergonomic ultrasound probe 
25. A system for objective measures of patient functions related to quality of life 
26. Weighing balance for Pharmaceutical industry 
27. Biomedical Health card design 
28. Electro Oculogram 
29. Electro Gustogram 
30. Plethysmography 
31. Automatic medicine announcement system 
32. Add on mixing chamber for mechanical ventilator 
33. Multi-IV Fluid feed system 
34. Pulse rate monitor 
35. Device Controller for Quadaplegics 
36. Short Range Medical Telemetry System 
37. Audible Thermometer 
38. Fiber optic transmission of biomedical parameters 
39. Colorimeter 
40. Patient monitoring system 
41. Blood gas analyzer 
42. Blood-flow meter 
43. Automatic Defibrillator 
44. EEG Monitor & Analyser 
45. ECG Monitor & Analyser 
46. EMG Monitor & Analyser 
47. Coordination Performance Tester 
48. Electro retinogram 
49. Telemetry With PC 
50. Internet Based Telemetry System 
51. Personal Identification and Verification Based on Multiple Biometric Features 
52. Face Detection Recognition and Tracking 
53. Personal Identification Based on Handwriting 
54. Biometric access control system 
55. Pre-processing of the iris image 
56. Biometric security system 
57. Personal Identification Based on Live Iris Recognition 
58. Human Gait Analysis and Recognition 
59. Treadmill 
60. MRI Phantom 
61. Thermal Therapy Device 
62. Depth of Anesthesia Monitor 
63. Biomedical Application for Virtual-Reality 
64. Interactive audiometer 
65. Spiro meter 
66. Blood gas analyzer 
67. Blood-flow meter 
68. Mind Switch 
69. Incubator 
70. Syringe infusion Pump 
71. Pacemaker 
72. Bio-Tele monitoring 
73. Heart Beat Monitor 
74. Respiration Monitor 
75. Pressure Monitor 
76. Drips Monitor 
77. Home Healthcare Device 
78. Calorimeter 
79. Sweat Measurement System 
80. Walking Distance Monitor 

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GSM BASED VEHICLE MONITORING &SECURITY SYSTEM PROJECT DOWNLOAD WITH SOURCE CODE

DEVELOPMENT OF A GSM BASED VEHICLE MONITORING &SECURITY SYSTEM|A GSM BASED VEHICLE MONITORING &SECURITY SYSTEM

 Aim 

Click here to view full download or contact us

The main aim of this project is to provide security to the vehicles. The system
automatically locks the vehicle as soon as it receives a predefined message from the user.

Applications Download 

using GPS tracking system we can detect the vehicle any where in the
global
automatic reduction of vehicle speed where an obstacle on the way to
present loss in an accident
diction of aichohol for a driver and limit the speed of the vechile not more
than 40km/hr

The GSM Modem supports popular "AT" command set so that users can develop

applications quickly

Uses GSM technology for following applications:

1. Access control devices: Access control devices can communicate with

servers and security staff through SMS messaging. Complete log of

transaction is available at the head-office Server instantly without any

wiring involved and device can instantly alert security personnel on their

mobile phone in case of any problem

2. Transaction terminals: EDC (Electronic Data Capturing) machines

can use SMS messaging to confirm transactions from central servers.

The main benefit is that central server can be anywhere in the world

3. Supply Chain Management: With a central server in your head office

with GSM capability, you can receive instant transaction data from

all your branch offices, warehouses and business associates with nil

downtime and low cost.

The control kit should be placed inside the vehicle far away from the temperature

Care should be taken such that all components in the control kit must be in

condition

Must and should specify the predefined messages in the source program

The gsm frequencys must be considered


The implementation of the project design can be divided in two parts.

− Hardware implementation

− Firmware implementation

Embedded Systems:

An embedded system can be defined as a computing device that does a specific focused job. Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine, mobile phone etc. are examples of embedded systems. Each of these appliances will have a processor and special hardware to meet the specific requirement of the application along with the embedded software that is executed by the processor for meeting that specific requirement. The embedded software is also called “firm ware”. The desktop/laptop computer is a general purpose computer. You can use it for a variety of applications such as playing games, word processing, accounting, software development and so on. In contrast, the software in the embedded systems is always fixed listed below:

· Embedded systems do a very specific task, they cannot be programmed to do different things. Embedded systems have very limited resources, particularly the memory. Generally, they do not have secondary storage devices such as the CDROM or the floppy disk. Embedded systems have to work against some deadlines. A specific job has to be completed within a specific time. In some embedded systems, called real-time systems, the deadlines are stringent. Missing a deadline may cause a catastrophe-loss of life or damage to property. Embedded systems are constrained for power. As many embedded systems operate through a battery, the power consumption has to be very low.

· Some embedded systems have to operate in extreme environmental conditions such as very high temperatures and humidity.

Following are the advantages of Embedded Systems:

1. They are designed to do a specific task and have real time performance constraints which must be met.
2. They allow the system hardware to be simplified so costs are reduced.
3. They are usually in the form of small computerized parts in larger devices which serve a general purpose.
4. The program instructions for embedded systems run with limited computer hardware resources, little memory and small or even non-existent keyboard or screen.

The Evolution of Mobile Telephone Systems

Cellular is one of the fastest growing and most demanding telecommunications applications. Today, it represents a continuously increasing percentage of all new telephone subscriptions around the world. Currently there are more than 45 million cellular subscribers worldwide, and nearly 50 percent of those subscribers are located in the United States.

The concept of cellular service is the use of low power transmitters where frequencies can be reused within a geographic area. The idea of cell based mobile radio service was formulated in the United States at Bell Labs in the early 1970s. Cellular systems began in the United States with the release of the advanced mobile phone service (AMPS) system in 1983. The AMPS standard was adopted by Asia, Latin America and Oceanic countries, creating the largest potential market in the world for cellular.

In the early 1980s, most mobile telephone systems were analog rather than digital, like today's newer systems. One challenge facing analog systems was the inability to handle the growing capacity needs in a cost efficient manner. As a result, digital technology was welcomed.

The advantages of digital systems over analog systems include ease of signaling, lower levels of interference, integration of transmission and switching and increased ability to meet capacity demands. The table below shows the worldwide development of mobile telephone systems.

The implementation of the project design can be divided in two parts.

-        Hardware implementation

-        Firmware implementation

Hardware implementation deals in drawing the schematic on the plane paper according to the application, testing the schematic design over the breadboard using the various IC’s to find if the design meets the objective, carrying out the PCB layout of the schematic tested on breadboard, finally preparing the board and testing the designed hardware.

The firmware part deals in programming the microcontroller so that it can control the operation of the IC’s used in the implementation. In the present work, we have used the Orcad design software for PCB circuit design, the Keil µv3 software development tool to write and compile the source code, which has been written in the C language. The Proload programmer has been used to write this compile code into the microcontroller. The firmware implementation is explained in the next chapter.

The project design and principle are explained in this chapter using the block diagram and circuit diagram. The block diagram discusses about the required components of the design and working condition is explained using circuit diagram and system wiring diagram.

Microcontrollers:

Microprocessors and microcontrollers are widely used in embedded systems products. Microcontroller is a programmable device. A microcontroller has a CPU in addition to a fixed amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed amount of on-chip ROM, RAM and number of I/O ports in microcontrollers makes them ideal for many applications in which cost and space are critical.

The Intel 8051 is Harvard architecture, single chip microcontroller (µC) which was developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s and early 1990s, but today it has largely been superseded by a vast range of enhanced devices with 8051-compatible processor cores that are manufactured by more than 20 independent manufacturers including Atmel, Infineon Technologies and Maxim Integrated Products.

8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. 8051 is available in different memory types such as UV-EPROM, Flash and NV-RAM. 

Features of AT89S52:

·        8K Bytes of Re-programmable Flash Memory.

·        RAM is 256 bytes.

·        4.0V to 5.5V Operating Range.

·        Fully Static Operation: 0 Hz to 33 MHz’s

·        Three-level Program Memory Lock.

·        256 x 8-bit Internal RAM.

·        32 Programmable I/O Lines.

·        Three 16-bit Timer/Counters.

·        Eight Interrupt Sources.

·        Full Duplex UART Serial Channel.

·        Low-power Idle and Power-down Modes.

·        Interrupt recovery from power down mode.

·        Watchdog timer.

·        Dual data pointer.

·        Power-off flag.

·        Fast programming time.

·        Flexible ISP programming (byte and page mode).

                                                                                           

Description:

The AT89s52 is a low-voltage, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable memory. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on chip flash allows the program memory to be reprogrammed in system or by a conventional non volatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89s52 is a powerful microcomputer, which provides a highly flexible and cost-effective solution to many embedded control applications.

In addition, the AT89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue the functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin description

Vcc    Pin 40 provides supply voltage to the chip. The voltage source is +5V.

GND   Pin 20 is the ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low-order

address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes during Program verification. External pull-ups are required during program verification     Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

                               Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. The port also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers      can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.

RST

Reset input A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP                                               

External Access Enable EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

UART

The Atmel 8051 Microcontrollers implement three general purpose, 16-bit timers/ counters. They are identified as Timer 0, Timer 1 and Timer 2 and can be independently configured to operate in a variety of modes as a timer or as an event counter. When operating as a timer, the timer/counter runs for a programmed length of time and then issues an interrupt request. When operating as a counter, the timer/counter counts negative transitions on an external pin. After a preset number of counts, the counter issues an interrupt request. The various operating modes of each timer/counter are described in the following sections.

A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit timer. Setting the run control bit (TRx) in TCON register turns the timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the timer/counter is unpredictable.

The C/T control bit (in TCON register) selects timer operation or counter operation, by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter is unpredictable. For timer operation (C/Tx# = 0), the timer register counts the divided-down peripheral clock. The timer register is incremented once every peripheral cycle (6 peripheral clock periods). The timer clock rate is FPER / 6, i.e. FOSC / 12 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. In addition to the “timer” or “counter” selection, Timer 0 and Timer 1 have four operating modes from which to select which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1and 2 are the same for both timer/counters. Mode 3 is different. 

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