Latest VLSI PROJECTS FREE DOWNLOAD WITH DOCUMENTATION

Latest VLSI PROJECTS FREE DOWNLOAD WITH DOCUMENTATION/VLSI PROJECTS 

1. A Novel Carry-Look ahead Approach to an Unified BCD and Binary Adder/ Subtractor
2. Speculative Carry Generation with Prefix Adder Using VHDL / Verilog
3. Improving Error Tolerance For Multithreaded Register Files
4. Higher Radix and Redundancy Factor for Floating Point Sort Division using VHDL/ Verilog
5. Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores using VHDL
6. Reconfigurable Architecture for Network Flow Analysis
7. The Reconfigurable Instruction Cell Array
8. System Architecture and Implementation of MIMO Sphere Decoders on FPGA
9. Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
10. Register for Phase Difference Based Logic
11. Designing Efficient Online Testable Reversible Adder with New Reversible Gate
12. High Speed Recursion Architecture for Map- Based Turbo Decoders
13. Concurrent Error Detection in Reed Solomon Encoders and Decoders
14. LFSR-Reseeding Scheme Achieving Low-Power Dissipation during Test
15. FPGA Implementation of Low Power Parallel Multiplier
16. Low Power Multiplier with Superious Power Suppression Technique
17. Abstraction and Refinement Techniques in Automated Design Debugging
18. Concurrent Error Detection in Reed Solomon Encoders and Decoders
19. Implementation of AES on A Dynamically Reconfigurable Architecture
20. Designing Efficient Online Testable Reversible Adder with New Reversible Gate
21. FPGA Implementation of Low Power Parallel Multiplier
22. Compact Hardware Design of Whirlpool Hashing Core
23. A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction
24. A High Efficiency fully Digital Synchrouns Buck Converter Power Delivery System Based on Finite State Machine
25. X-Masking During Logic BIST and Its Impact on Defect Coverage
26. New techniques for untreatable fault identification in sequential circuits
27. New and Improved BIST Diagnosis Method from combinatorial group testing theory
28. Energy Management for battery powered Reconfigurable computing platforms
29. Design specific path delay testing in look up table based FPGA
30. Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison
31. Improving Linear Test Data Compression
32. Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction
33. Extraction Error Modeling and Automated Model Debugging in High-Performance Custom Designs

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5:16 PM - By Admin 0

IEEE PROJECTS 2012 - 2013 FREE DOWNLOAD

DEPT OF ECE/EEE PROJECTS WITH BASE PAPER PAPER 

PRESENTATION TOPICS

Domain	IEEE Year	Updated	Download
Embedded Systems Projects | Real Time Projects | Hardware Projects
GPS / GIS	IEEE 2012	07-02-2013	Download
GSM / GPRS / CDMA	IEEE 2012	07-02-2013	Download
MEMS / Smart Sensors	IEEE 2012	07-02-2013	Download
Wireless Communication	IEEE 2012	07-02-2013	Download
Embedded Networking / Protocols	IEEE 2012	07-02-2013	Download
Biomedical / Biometrics	IEEE 2012	12-02-2013	Download
Robotic	IEEE 2012	12-02-2013	Download
EPLC / PLC / DCS / SCADA / HMI	IEEE 2012	12-02-2013	Download
Instrumentation / Virtual Instrumentation	IEEE 2012	12-02-2013	Download
Electrical / Power Electronics / Special Machines	IEEE 2012	12-02-2013	Download
RFID / Smart Cards / Magnetic Cards / Others	IEEE 2012	12-02-2013	Download
VLSI Design Projects | Real Time VLSI Projects |Hardware VLSI Projects | Simulation Projects
Real Time Projects in VLSI (ALTERA)	IEEE 2012	07-02-2013	Download
Real Time Projects in VLSI (Xilinx)	IEEE 2012	07-02-2013	Download
VLSI Simulation Projects	IEEE 2012	07-02-2013	Download
MATLAB Projects | Simulation Projects
Image Processing Projects	IEEE 2012	12-02-2013	Download
DSP Projects	IEEE 2012	12-02-2013	Download
Fuzzy Logic Projects	IEEE 2012	12-02-2013	Download
Neural Network Projects	IEEE 2012	12-02-2013	Download
ANFIS Projects (Adaptive Neuro-Fuzzy Inference Systems)	IEEE 2012	12-02-2013	Download
All in One Project Lists
Project List 1 (All Technologies)	IEEE 2012-12	12-02-2013	Download
Project List 2 (Only Embedded Projects)	IEEE 2012-12	05-10-2012	Download
Project List 3 (All Technologies)	IEEE 2012	07-11-2012	Download

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8:31 PM - By Admin 0

A VLSI ARCHITECTURE FOR VISIBLE WATERMARKING IN A SECURE STILL DIGITAL CAMERA (S2DC) DESIGN (CORRECTED)

INTRODUCTION

WATERMARKING is the process that embeds data called a watermark, a tag, or label into a multimedia object such that the watermark can be detected or extracted later to make an assertion about the object. The object may be an image, audio, video, or text. Whether the host data is in spatial domain, discrete cosine-transformed, or wavelet-transformed, watermarks of varying degree of visibility are added to present media as a guarantee of authenticity, ownership, source, and copyright protection. In general, any watermarking scheme (algorithm) consists of three parts, such as the following: 

1) watermark;

2) encoder (insertion algorithm);

3) decoder and comparator (verification or extraction or detection algorithm)

Whether each owner has a unique watermark or an owner wants to use different watermarks in different objects, the marking algorithm incorporates the watermark into the object. The verification algorithm authenticates the object determining both the owner and the integrity of the object. Watermarks and watermarking techniques can be divided into various categories. The watermarks can be applied either in spatial domain or in frequency domain. It has been pointed out that the frequency-domain methods are more robust than the spatial-domain techniques. On the other hand, the spatial domain watermarking schemes have less computational overhead compared with frequency-domain schemes. According to human perception, the digital watermarks can be divided into four categories:

1) visible; 

2) invisible-robust;

3) invisible-fragile;

4) dual. 

A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a casual viewer on careful inspection. The invisible-robust watermark is embedded in such a way that modifications made to the pixel value is perceptually not noticed, and it can be recovered only with appropriate decoding mechanism. The invisible-fragile watermark is embedded in such a way that any manipulation or modification of the image would alter or destroy the watermark. A dual watermark is a combination of a visible and an invisible watermark. In this type of watermark, an invisible watermark is used as a back-up for the visible watermark. 

VIDEO DEMO

http://www.youtube.com/watch?feature=player_embedded&v=ik-HUJckMLo

8:16 PM - By Admin 0

List of VLSI/VHDL Project titles for FYP/mini projects

1. •     DMA Controller (Direct Memory Access ) Using VHDL/VLSI
2. •     Edge detection using VHDL
3. •     Area-Efficient Universal Cryptography Processor for Smart Cards
4. •     The CSI Multimedia Architecture
5. •     VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPTAn
6. •     Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation
7. •     A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications
8. •     Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application
9. •     Implementation of IEEE 802.11 a Wlan Baseband Processor
10. •     A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
11. •     A Verilog Implementation of UART Design with Bist Capability
12. •     A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance
13. •     Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications
14. •     A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
15. •     A Low-Power Multiplier With The Spurious Power Suppression Technique
16. •     Design Of Reconfigurable Coprocessor for Communication Systems
17. •     Block-Based Multiperiod Dynamic Memory Design For Low Data-Retention Power
18. •     A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems
19. •     On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics
20. •     Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications
21. •     Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA
22. •     Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor
23. •     An Fpga-Based Architecture for Real Time Image Feature Extraction
24. •     Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
25. •     Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication
26. •     Fpga Based Power Efficient Channelizer for Software Defined Radio
27. •     FPGA Implementation(s) of a Scalable Encryption Algorithm.
28. •     Simulation Based Edge Detection.
29. •     A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
30. •     A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
31. •     A VLSI-BASED ROBOT DYNAMICS LEARNING ALGORITHM
32. •     An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation With Rf Output for SDR
33. •     BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
34. •     Hardware Algorithm for Variable Precision Multiplication on FPGA
35. •     Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
36. •     Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder
37. 
    

7:41 PM - By Reetha 0