DEVELOPMENT OF A GSM BASED VEHICLE MONITORING &SECURITY SYSTEM|A GSM BASED VEHICLE MONITORING &SECURITY SYSTEM
Aim
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The main aim of this project is to provide security to the vehicles. The system
automatically locks the vehicle as soon as it receives a predefined message from the user.
Applications Download
using GPS tracking system we can detect the vehicle any where in the
global
automatic reduction of vehicle speed where an obstacle on the way to
present loss in an accident
diction of aichohol for a driver and limit the speed of the vechile not more
than 40km/hr
The GSM Modem supports popular "AT" command set so that users can develop
applications quickly
Uses GSM technology for following applications:
1. Access control devices: Access control devices can communicate with
servers and security staff through SMS messaging. Complete log of
transaction is available at the head-office Server instantly without any
wiring involved and device can instantly alert security personnel on their
mobile phone in case of any problem
2. Transaction terminals: EDC (Electronic Data Capturing) machines
can use SMS messaging to confirm transactions from central servers.
The main benefit is that central server can be anywhere in the world
3. Supply Chain Management: With a central server in your head office
with GSM capability, you can receive instant transaction data from
all your branch offices, warehouses and business associates with nil
downtime and low cost.
The control kit should be placed inside the vehicle far away from the temperature
Care should be taken such that all components in the control kit must be in
condition
Must and should specify the predefined messages in the source program
The gsm frequencys must be considered
The implementation of the project design can be divided in two parts.
− Hardware implementation
− Firmware implementation
Embedded Systems:
An embedded system can be defined as a computing
device that does a specific focused job. Appliances such as the
air-conditioner, VCD player, DVD player, printer, fax machine, mobile phone
etc. are examples of embedded systems. Each of these appliances will have a
processor and special hardware to meet the specific requirement of the
application along with the embedded software that is executed by the processor
for meeting that specific requirement. The embedded software is also called
“firm ware”. The desktop/laptop computer is a general purpose computer. You can
use it for a variety of applications such as playing games, word processing,
accounting, software development and so on. In contrast, the software in the
embedded systems is always fixed listed below:
· Embedded systems do a very
specific task, they cannot be programmed to do different things. Embedded
systems have very limited resources, particularly the memory. Generally, they
do not have secondary storage devices such as the CDROM or the floppy disk.
Embedded systems have to work against some deadlines. A specific job has to be
completed within a specific time. In some embedded systems, called real-time
systems, the deadlines are stringent. Missing a deadline may cause a
catastrophe-loss of life or damage to property. Embedded systems are
constrained for power. As many embedded systems operate through a battery, the
power consumption has to be very low.
· Some embedded systems have to
operate in extreme environmental conditions such as very high temperatures and
humidity.
Following are the advantages of Embedded Systems:
- They are designed to do a specific task and have real time performance constraints which must be met.
- They allow the system hardware to be simplified so costs are reduced.
- They are usually in the form of small computerized parts in larger devices which serve a general purpose.
- The program instructions for embedded systems run with limited computer hardware resources, little memory and small or even non-existent keyboard or screen.
The Evolution of Mobile Telephone Systems
Cellular is one
of the fastest growing and most demanding telecommunications applications.
Today, it represents a continuously increasing percentage of all new telephone
subscriptions around the world. Currently there are more than 45 million cellular
subscribers worldwide, and nearly 50 percent of those subscribers are located
in the United States .
The concept of cellular service
is the use of low power transmitters where frequencies can be reused within a
geographic area. The idea of cell based mobile radio service was formulated in
the United States
at Bell Labs in the early 1970s. Cellular systems began in the United States
with the release of the advanced mobile phone service (AMPS) system in 1983.
The AMPS standard was adopted by Asia, Latin America
and Oceanic countries, creating the largest potential market in the world for
cellular.
In the early 1980s, most mobile
telephone systems were analog rather than digital, like today's newer systems.
One challenge facing analog systems was the inability to handle the growing
capacity needs in a cost efficient manner. As a result, digital technology was
welcomed.
The advantages of digital
systems over analog systems include ease of signaling, lower levels of
interference, integration of transmission and switching and increased ability
to meet capacity demands. The table
below shows the worldwide development of mobile telephone systems.
The implementation of the project design can be
divided in two parts.
-
Hardware implementation
-
Firmware implementation
Hardware implementation deals in drawing the
schematic on the plane paper according to the application, testing the
schematic design over the breadboard using the various IC’s to find if the
design meets the objective, carrying out the PCB layout of the schematic tested
on breadboard, finally preparing the board and testing the designed hardware.
The firmware
part deals in programming the microcontroller so that it can control the
operation of the IC’s used in the implementation. In the present work, we have
used the Orcad design software for PCB circuit design, the Keil µv3 software
development tool to write and compile the source code, which has been written
in the C language. The Proload programmer has been used to write this compile
code into the microcontroller. The firmware implementation is explained in the
next chapter.
The project design and principle are
explained in this chapter using the block diagram and circuit diagram. The
block diagram discusses about the required components of the design and working
condition is explained using circuit diagram and system wiring diagram.
Microcontrollers:
Microprocessors and microcontrollers
are widely used in embedded systems products. Microcontroller is a programmable device. A microcontroller has a CPU
in addition to a fixed amount of RAM, ROM, I/O ports and a timer embedded all
on a single chip. The fixed amount of on-chip ROM, RAM and number of I/O ports
in microcontrollers makes them ideal for many applications in which cost and
space are critical.
The Intel
8051 is Harvard architecture, single chip microcontroller (µC) which was
developed by Intel in 1980 for use in embedded systems. It was popular in the
1980s and early 1990s, but today it has largely been superseded by a vast range
of enhanced devices with 8051-compatible processor cores that are manufactured
by more than 20 independent manufacturers including Atmel, Infineon
Technologies and Maxim Integrated Products.
8051 is an
8-bit processor, meaning that the CPU can work on only 8 bits of data at a
time. Data larger than 8 bits has to be broken into 8-bit pieces to be
processed by the CPU. 8051 is available in different memory types such as
UV-EPROM, Flash and NV-RAM.
Features of AT89S52:
·
8K Bytes of Re-programmable Flash
Memory.
·
RAM is 256 bytes.
·
4.0V to 5.5V Operating Range.
·
Fully Static Operation: 0 Hz to
33 MHz’s
·
Three-level Program Memory Lock.
·
256 x 8-bit Internal RAM.
·
32 Programmable I/O Lines.
·
Three 16-bit Timer/Counters.
·
Eight Interrupt Sources.
·
Full Duplex UART Serial Channel.
·
Low-power Idle and Power-down
Modes.
·
Interrupt recovery from power
down mode.
·
Watchdog timer.
·
Dual data pointer.
·
Power-off flag.
·
Fast programming time.
·
Flexible ISP programming (byte
and page mode).
Description:
The AT89s52 is a low-voltage, high-performance CMOS 8-bit microcomputer
with 8K bytes of Flash programmable memory. The device is manufactured using
Atmel’s high density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The on chip flash allows the program
memory to be reprogrammed in system or by a conventional non volatile memory
programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip,
the Atmel AT89s52 is a powerful microcomputer, which provides a highly flexible
and cost-effective solution to many embedded control applications.
In addition, the AT89s52 is
designed with static logic for operation down to zero frequency and supports
two software selectable power saving modes. The Idle Mode stops the CPU while
allowing the RAM, timer/counters, serial port and interrupt system to continue
the functioning. The power-down mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset.
Pin description
Vcc Pin 40 provides supply voltage to the chip. The voltage source is +5V.
GND Pin 20 is the ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s are written to port 0
pins, the pins can be used as high impedance inputs. Port 0 can also be
configured to be the multiplexed low-order
address/data bus during accesses to external program and data memory.
In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and
outputs the code bytes during Program verification. External pull-ups are
required during program verification Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The
Port 1 output buffers can sink/source four TTL inputs. When 1s are written to
Port 1 pins, they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can
be configured to be the timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the
following table.
Port 1 also receives the low-order address bytes during Flash
programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The
Port 2 output buffers can sink/source four TTL inputs. When 1s are written to
Port 2 pins, they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that uses 16-bit
addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that uses
8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register. The port also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) because
of the pull-ups. Port 3 receives some control signals for Flash programming and
verification.
Port 3 also serves the functions of various special features of the
AT89S52, as shown in the following table.
RST
Reset input A high on this pin for two machine cycles while the oscillator is
running resets the device. This pin drives high for 98 oscillator periods after
the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to
disable this feature. In the default state of bit DISRTO, the RESET HIGH out
feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency and may be used for external timing or clocking purposes.
Note, however, that one ALE pulse is skipped during each access to external
data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR
location 8EH. With the bit set, ALE is active only during a MOVX or MOVC
instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable
bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52
is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory.
EA/VPP
External Access Enable EA must be strapped to GND in
order to enable the device to fetch code from external program memory locations
starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed,
EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin
also receives the 12-volt programming enable voltage (VPP) during Flash
programming.
XTAL1
Input to the inverting oscillator
amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting
oscillator amplifier.
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier that can be configured for use as an on-chip oscillator. Either a
quartz crystal or ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is driven.
There are no requirements on the duty cycle of the external clock signal, since
the input to the internal clocking circuitry is through a divide-by-two
flip-flop, but minimum and maximum voltage high and low time specifications
must be observed.
UART
The Atmel 8051 Microcontrollers implement three
general purpose, 16-bit timers/ counters. They are identified as Timer 0, Timer
1 and Timer 2 and can be independently configured to operate in a variety of
modes as a timer or as an event counter. When operating as a timer, the
timer/counter runs for a programmed length of time and then issues an interrupt
request. When operating as a counter, the timer/counter counts negative
transitions on an external pin. After a preset number of counts, the counter
issues an interrupt request. The various operating modes of each timer/counter
are described in the following sections.
A basic operation consists of timer registers THx and
TLx (x= 0, 1) connected in cascade to form a 16-bit timer. Setting the run
control bit (TRx) in TCON register turns the timer on by allowing the selected
input to increment TLx. When TLx overflows it increments THx; when THx
overflows it sets the timer overflow flag (TFx) in TCON register. Setting the
TRx does not clear the THx and TLx timer registers. Timer registers can be
accessed to obtain the current count or to enter preset values. They can be
read at any time but TRx bit must be cleared to preset their values, otherwise
the behavior of the timer/counter is unpredictable.
The C/T control bit (in TCON register) selects timer
operation or counter operation, by selecting the divided-down peripheral clock
or external pin Tx as the source for the counted signal. TRx bit must be
cleared when changing the mode of operation, otherwise the behavior of the
timer/counter is unpredictable. For timer operation (C/Tx# = 0), the timer
register counts the divided-down peripheral clock. The timer register is
incremented once every peripheral cycle (6 peripheral clock periods). The timer
clock rate is FPER / 6, i.e. FOSC / 12 mode. There are no restrictions on the
duty cycle of the external input signal, but to ensure that a given level is
sampled at least once before it changes, it should be held for at least one
full peripheral cycle. In addition to the “timer” or “counter” selection, Timer
0 and Timer 1 have four operating modes from which to select which are selected
by bit-pairs (M1, M0) in TMOD. Modes 0, 1and 2 are the same for both
timer/counters. Mode 3 is different.
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